The present invention relates to a test circuit of a semiconductor integrated circuit, in particular, to a semiconductor device in which a test circuit is incorporated in a semiconductor chip and a chip size affects the area (in particular, a wiring area) of the test circuit.
The integration degree of the device in a semiconductor integrated circuit has been improved more and more, and the semiconductor integrated circuit has also become more complicated along with such improvement. As a consequence, for example, test time for evaluating the validity of the semiconductor integrated circuit in the development of products has increased. On the other hand, in order to reduce the development cost of the semiconductor integrated circuit and realize a cost reduction of the product, it becomes necessary to improve the evaluation efficiency of the semiconductor integrated circuit and to decrease the test time of the development of products.
Recently, in the development of products, at the design stage, the circuit to be tested (the circuit the operation of which is worried, and the circuit with which a special operation is desired to be conducted) has a plurality of different characteristics (or operations) and the semiconductor integrated circuit is designed so that the plurality of these characteristics can be selected.
That is, when one circuit has a plurality of characteristics in advance, a plurality of characteristics can be tested with respect to one circuit only by manufacturing one semiconductor chip (semiconductor device), and the evaluation efficiency of the semiconductor integrated circuit is improved.
Specifically, a switching circuit which is capable of switching over the characteristics (or operations) of the circuit to be tested is arranged in the semiconductor chip, and the switching circuit is controlled with a test select signal. Furthermore, the test select signal is created with the test circuit. That is, a test mode entry signal for the entry into the test mode is input to the test circuit at a special timing which is different from the normal timing. Then, in the test circuit, since the test mode is recognized, the test decode signal is latched with the test code latch circuit so that the test select signal is created.